1. Field of the Invention
This invention relates generally to semiconductor fabrication, and more particularly to methods of forming capacitor electrodes for integrated circuit memory cells.
2. Description of the Related Art
Device scaling in integrated circuit design has produced an attendant decrease in the available wafer areas for devices, such as dynamic random access memory cells (xe2x80x9cDRAMsxe2x80x9d). As a consequence, memory cell capacitors must be squeezed into ever shrinking spaces. Because the capacitance of a memory cell capacitor is proportional to the surface area of the capacitor electrodes, the job of maintaining or even increasing device capacitance while minimum geometries continue to shrink is difficult. Because DRAM memory cell operation typically improves with increased capacitance, a variety of methods have been developed in an attempt to if increase storage electrode surface areas while at the same time maintaining or reducing wafer area taken up by a memory cell. Examples of electrode designs having greater surface area include trench and stacked capacitor configurations as well as cylindrical and finned capacitor configurations.
One method for increasing electrode surface area involves the formation of an electrode with a roughened or irregular outer surface. Methods for providing a roughened electrode surface include those employing hemispherical grain (xe2x80x9cHSGxe2x80x9d) silicon. In this method, a memory cell access transistor is formed on a semiconductor substrate. An insulating layer is then formed on the substrate and the access transistor. A doped amorphous silicon layer is then formed on the insulating layer, frequently by reacting a silicon source gas such as silane (SiH4) or disilane (Si2H6) with a dopant gas such as phosphine (PH3).
Next, a hemispherical grained surface is formed on the doped silicon layer. There are a number of different methods known in the art for forming an HSG silicon film, including by gas-phased nucleation and surface seeding. In the first method, a doped amorphous silicon layer is subjected to a vacuum anneal to redistribute silicon atoms in the amorphous silicon layer to form hemispherical grains of polysilicon. In the second alternative, an amorphous silicon layer is processed at a temperature of about 550xc2x0 C. to about 600xc2x0 C. and exposed to a silicon gas source so as to form silicon nuclei on the amorphous layer. This structure may then be annealed in the absence of the silicon gas source to grow silicon nuclei and form the HSG polysilicon film.
Polysilicon storage cells or electrodes are provided with n-type or p-type dopants as a means of increasing their capacitance and DRAM performance. Although the use of dopants such as phosphorus is desirable from a device operation standpoint, there are certain manufacturing drawbacks. For example, out-diffusion of dopant from a doped silicon layer may occur during subsequent high temperature steps and lead to thickness fluctuations in deposited capacitor dielectric films. Controlling fluctuation in capacitor dielectric thickness is desirable because the thickness of the dielectric dictates the amount of charge that may be stored without damaging the capacitor. The capacitor dielectric is advantageously formed with a thickness that is as small as possible, but that still avoids dielectric breakdown. Furthermore, the unwanted migration of phosphorus may also adversely affect HSG growth. The mechanism is thought to be the result of dopant atoms forming a resistant path to the autodiffusion of surface amorphous silicon atoms. The problem of out-diffusion may be more prevalent in circumstances where a doped silicon layer is formed on both the front side and the backside of the wafer.
One method of improving uniformity of silicon nitride capacitor dielectric deposition from batch to batch is to reduce the number of wafers in a reactor chamber batch. However, reduction of the number of wafers in each furnace load (such as from 6 lots to 4 lots) typically results in logistics and throughput difficulties during, for example, nitride deposition.
In accordance with one aspect of the present invention, a method of forming hemispherical grain silicon on a substrate is provided that includes forming a first doped silicon layer on the substrate and forming a first undoped amorphous silicon barrier layer on the doped silicon layer. A hemispherical grain silicon layer is formed on the undoped amorphous silicon barrier layer.
In accordance with another aspect of the present invention, a method of forming a memory cell storage electrode on substrate is provided that includes forming a first doped silicon layer on the substrate and forming a first undoped amorphous silicon barrier layer on the doped silicon layer. A hemispherical grain silicon layer is formed on the undoped amorphous silicon barrier layer and a capacitor dielectric layer is formed on the hemispherical grain silicon layer.
In accordance with another aspect of the present invention, a method of forming hemispherical grain silicon on a substrate having a front side and a backside is provided that includes forming a first doped silicon layer on the front side and a second doped silicon layer on the backside and forming a first barrier layer on the first doped silicon layer and a second barrier layer on the second doped silicon layer. A hemispherical grain silicon layer is formed on the first doped silicon layer.
In accordance with another aspect of the present invention, a method of forming a memory cell capacitor on a substrate is provided that includes forming a first doped silicon layer on the substrate and a first undoped amorphous silicon barrier layer on the first doped silicon layer. A hemispherical grain silicon layer is formed on the first undoped amorphous silicon barrier layer. A capacitor dielectric layer is formed on the hemispherical grain silicon layer and a top electrode is formed on the capacitor dielectric.
In accordance with another aspect of the present invention, a method of forming hemispherical grain silicon on a substrate is provided that includes forming a first doped silicon layer on the substrate and a-first oxide barrier layer on the doped silicon layer. The first oxide layer and the first doped silicon layer are patterned into a desired shape. The first oxide barrier layer is removed and a hemispherical grain silicon layer is formed on the first doped silicon layer.